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d a t a sh eet product speci?cation supersedes data of 1997 jun 10 file under integrated circuits, ic17 1997 sep 03 integrated circuits UMA1015AM low-power dual frequency synthesizer for radio communications
1997 sep 03 2 philips semiconductors product speci?cation low-power dual frequency synthesizer for radio communications UMA1015AM features two fully programmable rf dividers up to 1.1 ghz fully programmable reference divider up to 35 mhz 2 : 1 or 1 : 1 ratio of selectable reference frequencies fast three-line serial bus interface adjustable phase comparator gain programmable out-of-lock indication for both loops on-chip voltage doubler low current consumption from 3 v supply separate power-down mode for each synthesizer up to 4 open-drain output ports crystal input frequency signal inverted and buffered output on separate pin. applications cordless telephone hand-held mobile radio. general description the UMA1015AM is a low-power dual frequency synthesizer for radio communications which operates in the 50 to 1100 mhz frequency range. each synthesizer consists of a fully programmable main divider, a phase and frequency detector and a charge pump. there is a fully programmable reference divider common to both synthesizers which operates up to 35 mhz. the device is programmed via a 3-wire serial bus which operates up to 10 mhz. the charge pump currents (gains) are fixed by an external resistance at pin 20 (i set ). the bicmos device is designed to operate from 2.7 v (3 nicd cells) to 5.5 v at low current. digital supplies v dd1 and v dd2 must be at the same potential. the charge pump supply (v cc ) can be provided by an external source or on-chip voltage doubler. v cc must be equal to or higher than v dd1 . each synthesizer can be powered-down independently via the serial bus to save current. it is also possible to power-down the device via the hpd input (pin 5). quick reference data symbol parameter conditions min. typ. max. unit v dd1 , v dd2 digital supply voltage v dd1 =v dd2 2.7 - 5.5 v v cc charge pump supply voltage external supply; doubler disabled; v cc 3 v dd 2.7 - 6.0 v v ccvd charge pump supply from voltage doubler doubler enabled - 2v dd1 - 0.6 6.0 v i dd1 +i dd2 +i cc operating supply current both synthesizers on; doubler disabled; v dd1 =v dd2 =3v - 8.7 - ma i ddpd +i ccpd total current in power-down mode doubler disabled; v dd1 =v dd2 =3v - 3 -m a i ddpd current in power-down mode from supply v dd1 and v dd2 doubler enabled; v dd1 =v dd2 =3v - 0.25 - ma f rf rf input frequency for each synthesizer 50 - 1100 mhz f xtalin crystal input frequency 3 - 35 mhz f pc(min) minimum phase comparator frequency - 10 - khz f pc(max) maximum phase comparator frequency - 750 - khz t amb operating ambient temperature - 30 - +85 c
1997 sep 03 3 philips semiconductors product speci?cation low-power dual frequency synthesizer for radio communications UMA1015AM ordering information block diagram type number package name description version UMA1015AM ssop20 plastic shrink small outline package; 20 leads; body width 4.4 mm sot266-1 fig.1 block diagram. handbook, full pagewidth mgg523 4-bit shift register control latch power down ool select current ratio port bits 17-bit shift register latch main divider tool a rfa/64 latch main divider tool b rfb/64 latch reference divider div by 2 address decoder phase detector lock detector phase detector lock detector lock select tool a tool b pump bias voltage doubler sr synthesizer a synthesizer b 11 12 13 6 5 10 8 15 4 14 7 16 20 18 3 19 1 2 9 17 clk data e rfa hpd f xtalo f xtalin rfb v dd1 v dd2 dgnd agnd i set v cc cpa p0/ool p1 p2 p3 cpb vdb enable rf/64 phase error phase error UMA1015AM
1997 sep 03 4 philips semiconductors product speci?cation low-power dual frequency synthesizer for radio communications UMA1015AM pinning symbol pin description p1 1 output port 1 p2 2 output port 2 cpa 3 charge pump output synthesizer a v dd1 4 digital supply voltage 1 hpd 5 hardware power-down (input low = power-down) rfa 6 rf input synthesizer a dgnd 7 digital ground f xtalin 8 common crystal frequency input from tcxo p3 9 output port 3 f xtalo 10 open-drain output of f xtal signal clk 11 programming bus clock input data 12 programming bus data input e 13 programming bus enable input (active low) v dd2 14 digital supply voltage 2 rfb 15 rf input synthesizer b agnd 16 analog ground to charge pumps cpb 17 charge pump output synthesizer b v cc 18 analog supply to charge pump; external or voltage doubler output p0/ool 19 port output 0/out-of-lock output i set 20 regulator pin to set charge pump currents fig.2 pin configuration. handbook, halfpage p1 p2 cpa v dd1 hpd rfa dgnd f xtalin p3 f xtalo i set p0/ool v cc cpb rfb v dd2 agnd e data clk 1 2 3 4 5 6 7 8 9 10 11 12 20 19 18 17 16 15 14 13 UMA1015AM mgg522 functional description main dividers each synthesizer has a fully programmable 17-bit main divider. the rf input drives a pre-amplifier to provide the clock to the first divider bit. the pre-amplifier has a high input impedance, dominated by pin and pad capacitance. the circuit operates with signal levels from below 50 mv (rms) up to 250 mv (rms), and at frequencies up to 1.1 ghz. the high frequency sections of the divider are implemented using bipolar transistors, while the slower section uses cmos technology. the range of division ratios is 512 to 131071. reference divider there is a common fully programmable 12-bit reference divider for the two synthesizers. the input f xtalin drives a pre-amplifier to provide the clock input for the reference divider. this clock signal is also inverted and output on pin f xtalo (open drain). a crystal connected between f xtalin and f xtalo with suitable feedback components can be used to make an oscillator. an extra divide-by-2 block allows a reference comparison frequency for synthesizer b to be half the frequency of synthesizer a. this feature is selectable using the program bit sr. if the programmed reference divider ratio is r then the ratio for each synthesizer is as given in table 1. the range for the division ratio r is 8 to 4095. opposite edges of the divider output are used to drive the phase detectors to ensure that active edges arrive at the phase detectors of each synthesizer at different times. this minimizes the potential for interference between the charge pumps of each loop. the reference divider consists of cmos devices operating beyond 35 mhz.
1997 sep 03 5 philips semiconductors product speci?cation low-power dual frequency synthesizer for radio communications UMA1015AM table 1 synthesizer ratio of reference divider phase comparators for each synthesizer, the outputs of the main and reference dividers drive a phase comparator where a charge pump produces phase error current pulses for integration in an external loop filter. the charge pump current is set by an external resistance r set at pin i set , where a temperature-independent voltage of 1.1 v is generated. r set should be between 12 and 60 k w . the charge pump current, i cp , can be programmed to be either (12 i set ) or (24 i set ) with a maximum of 2.3 ma. the dead zone, caused by finite switching of current pulses, is cancelled by an internal delay in the phase detector thus giving improved linearity. the charge pump has a separate supply, v cc , which helps to reduce the interference on the charge pump output from other parts of the circuit. v cc can be higher than v dd1 if a wider range on the vco input is required. v cc must not be less than v dd1 . voltage doubler if required, there is a voltage doubler on-chip to supply the charge pumps at a higher level than the nominal available supply. the doubler operates from the digital supply v dd1 , and is internally limited to a maximum output of 6 v. an external capacitor is required on pin v cc for smoothing, the capacitor required to develop the extra voltage is integrated on-chip. to minimize the noise being introduced to the charge pump output from the voltage doubler, the doubler clock is suppressed (provided both loops are in-lock) for the short time that the charge pumps are active. the doubler clock (rf/64) is derived from whichever main divider is operating (synthesizer a has priority). while both synthesizers are powered down (and the doubler is enabled), the doubler clock is supplied by a low-current internal oscillator. the doubler can be disabled by programming the bit vdon to logic 0, in order to allow an external charge pump supply to be used. out-of-lock indication/output ports there is a common lock detector on-chip for the synthesizers. the lock condition of each, or both loops, is output via an open-drain transistor which drives pin p0/ool (when out-of-lock, the transistor is turned on and therefore the output is forced low). the lock condition output is software selectable (see table 4). sr synthesizer a synthesizer b 0r r 1r 2r an out-of-lock condition is flagged when the phase error is greater than t ool , which is approximately 30 ns. the out-of-lock flag is only released after the first reference cycle where the phase error is less than t ool . the out-of-lock function can be disabled, via the serial bus, and the pin p0/ool can be used as a port output. three other port outputs p1, p2 and p3 (open-drain transistors) are also available. serial programming bus a simple 3-line unidirectional serial bus is used to program the circuit. the 3 lines are data, clk and e (enable). the data sent to the device is loaded in bursts framed by e. programming clock edges are ignored until e goes active low. the programmed information is loaded into the addressed latch when e returns inactive (high). this is allowed when clk is in either state without causing any consequences to the register data. only the last 21 bits serially clocked into the device are retained within the programming register. additional leading bits are ignored, and no check is made on the number of clock pulses. the fully static cmos design uses virtually no current when the bus is inactive. it can always capture new programming data even during power-down of both synthesizers. however when either synthesizer a or synthesizer b or both are powered-on, the presence of a tcxo signal is required at pin 8 (f xtalin ) for correct programming. data format data is entered with the most significant bit first. the leading bits make up the data field, while the trailing four bits are an address field. the address bits are decoded on the rising edge of e. this produces an internal load pulse to store the data in the addressed latch. to ensure that data is correctly loaded on first power-up, e should be held low and only taken high after having programmed an appropriate register. to avoid erroneous divider ratios, the pulse is inhibited during the period when data is read by the frequency dividers. this condition is guaranteed by respecting a minimum e pulse width after data transfer. the data format and register bit allocations are shown in table 2.
1997 sep 03 6 philips semiconductors product speci?cation low-power dual frequency synthesizer for radio communications UMA1015AM table 2 bit allocation note 1. the test register should not be programmed with any other values except all zeros for normal operation. table 3 bit allocation description table 4 out-of-lock select first register bit allocation last p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 p16 p17 p18 p19 p20 p21 dt16 dt15 dt14 dt13 dt12 data field dt4 dt3 dt2 dt1 dt0 address x x vdon po ola olb cra crb x x spda spdb p3 p2 p1 x x 0 0 0 1 ma16 synthesizer a main divider coefficient ma0 0 1 0 0 0 0 0 0 sr r11 reference divider coefficient r0 0 1 0 1 mb16 synthesizer b main divider coefficient mb0 0 1 1 0 reserved for test (1) 000 0 0 00 000000 0 0 0 00 spbf 0 0 1 0 0 0 symbol description spda, spdb software power-down for synthesizers a and b (0 = power-down) spbf software power-on for f xtal buffer (1 = buffer on) p3, p2, p1 and p0 bits output to pins 1, 2, 9 and 19 (1 = high impedance) vdon voltage doubler enable (1 = doubler enabled) ola, olb out-of-lock select; selects signal output to pin 19 (see table 4) cra, crb charge pump a/b current to i set ratio select (see table 5) sr reference frequency ratio select (see table 6) ola olb output at pin 19 00p0 0 1 lock status of loop b; oolb 1 0 lock status of loop a; oola 1 1 logic or function of loops a and b
1997 sep 03 7 philips semiconductors product speci?cation low-power dual frequency synthesizer for radio communications UMA1015AM table 5 charge pump current ratio table 6 reference division ratio power-down modes the device can be powered down either via pin hpd (active low = power-down) or via the serial bus (bits spda and spdb, logic 0 = power-down). cra/crb current at pump 0i cp =12 i set 1i cp =24 i set sr synthesizer a synthesizer b 0r r 1r 2r the synthesizers are powered up when both hardware and software power-down signals are at logic 1. when only one synthesizer is powered down, the functions common to both will be maintained (independent of the state of spbf). when both synthesizers are powered down, the f xtal buffer can be maintained in an active state by setting spbf to logic 1. this will allow any system clock derived from the f xtalo buffered output to remain on in power-down. note that spbf is independent of the state of hpd. when both synthesizers are switched off, the voltage doubler (if enabled) will remain active drawing a reduced current. an internal oscillator will drive the doubler in this situation. if both synthesizers have been in a power-down condition, then when one or both synthesizers are reactivated, the reference and main dividers restart in such a way as to avoid large random phase errors at the phase comparator. limiting values in accordance with the absolute maximum rating system (iec 134). handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling mos devices. symbol parameter min. max. unit v dd1 , v dd2 dc range of digital power supply voltage with respect to dgnd - 0.3 +6.0 v v cc dc charge pump supply voltage with respect to agnd - 0.3 +6.0 v d v cc-dd difference in voltage between v cc and v dd1 , v dd2 - 0.3 +6.0 v v n dc voltage at pins 1, 2, 5, 6, 8 to 15, 19 and 20 with respect to dgnd - 0.3 v dd1 + 0.3 v v 3, 17 dc voltage at pins 3 and 17 with respect to agnd - 0.3 v cc + 0.3 v d v gnd difference in voltage between agnd and dgnd (these pins should be connected together) - 0.3 +0.3 v t stg storage temperature - 55 +125 c t amb operating ambient temperature - 30 +85 c
1997 sep 03 8 philips semiconductors product speci?cation low-power dual frequency synthesizer for radio communications UMA1015AM characteristics v dd1 =v dd2 = 2.7 to 5.5 v; v cc = 2.7 to 6.0 v; t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies; (v dd1 , v dd2 and v cc ) voltage doubler disabled, external supply on v cc v dd1 , v dd2 digital supply voltage v dd1 =v dd2 2.7 - 5.5 v i dd1 +i dd2 total digital supply current from v dd1 and v dd2 f xtal = 12.8 mhz; both synthesizers on; v dd1 =v dd2 =3v - 8.7 - ma f xtal = 12.8 mhz; both synthesizers on; v dd1 =v dd2 = 5.5 v -- 12.5 ma i ddpda , i ddpdb total digital supply current from v dd1 and v dd2 with one synthesizer in power-down mode f xtal = 12.8 mhz; one synthesizer powered down; v dd1 =v dd2 =3v - 5.0 - ma f xtal = 12.8 mhz; one synthesizer powered down; v dd1 =v dd2 = 5.5 v -- 7.5 ma i dd(xtal) digital supply current from v dd1 with both synthesizers powered down and crystal buffer on f xtal = 12.8 mhz; v hpd =0v; spbf = 1; v dd1 =v dd2 =3v - 0.5 - ma f xtal = 12.8 mhz; v hpd =0v; spbf = 1; v dd1 =v dd2 = 5.5 v -- 1.15 ma i ddpd digital supply current in power-down mode both synthesizers powered down; v hpd = 0 v; spbf = 0 -- 60 m a v cc charge pump supply voltage v cc 3 v dd 2.7 - 6.0 v i cc charge pump supply current both synthesizers on and in lock; f ref = 12.5 khz -- 25 m a i ccpd charge pump supply current in power-down mode both synthesizers powered down -- 25 m a voltage doubler enabled i dd total digital supply current from v dd1 and v dd2 f xtal = 12.8 mhz; both synthesizers on and in lock; v dd1 =3v; f rf = 900 mhz - 9.2 12 ma i ddpd total digital supply current in power-down mode from v dd1 and v dd2 both synthesizers powered down; v dd1 =3v; v hpd =0v; spbf = 0 - 0.25 0.4 ma v ccvd charge pump supply voltage dc current drawn from v cc =50 m a; f rf > 100 mhz 4.2 2v dd1 - 0.6 6.0 v
1997 sep 03 9 philips semiconductors product speci?cation low-power dual frequency synthesizer for radio communications UMA1015AM rf main divider input; rfa and rfb f rf rf input frequency 50 - 1100 mhz v rf(rms) rf input signal voltage (rms value; ac coupled) r s =50 w; f rf = 400 to 1100 mhz 50 - 250 mv r s =50 w; f rf = 80 to 400 mhz 150 - 400 mv r s =50 w; f rf = 50 to 80 mhz 225 - 400 mv z i input impedance (real part) f rf = 1 ghz; indicative, not tested - 300 -w c i input capacitance indicative, not tested - 1 - pf r pm principle main divider ratio 512 - 131071 reference divider input; f xtalin f xtalin reference input frequency from crystal 3 - 35 mhz v xtalin(rms) sinusoidal input voltage (rms value) 100 - 500 mv z i input impedance (real part) f xtalin = 12.8 mhz; indicative, not tested - 10 - k w c i input capacitance indicative, not tested - 1 - pf r rd reference divider ratio 8 - 4095 charge pump current setting resistor input; i set v set voltage output on i set r set =12to60k w- 1.1 - v charge pump outputs; cpa and cpb i cp charge pump sink or source current r set =15k w ; cra/crb = logic 1; i cp =i set 24; v cp =0.4vtov cc - 0.5 v 1.3 1.75 2.3 ma r set =15k w ; cra/crb = logic 0; i cp =i set 12; v cp =0.4vtov cc - 0.5 v 0.7 0.9 1.2 ma i li charge pump off leakage current v cp =0.4vtov cc - 0.5 v - 5 1+5na logic input signal levels; data, clk, e and hpd v ih high level input voltage at logic 1 0.7v dd1 - v dd1 + 0.3 v v il low level input voltage at logic 0 - 0.3 - 0.3v dd1 v i bias input bias currents at logic 1 or logic 0 - 5 - +5 m a c i input capacitance indicative, not tested - 1 - pf port outputs/out-of-lock; p0/ool, p1, p2, p3 and f xtalo - open drain outputs v ol low level output voltage i sink < 0.4 ma -- 0.4 v symbol parameter conditions min. typ. max. unit
1997 sep 03 10 philips semiconductors product speci?cation low-power dual frequency synthesizer for radio communications UMA1015AM serial timing characteristics v dd1 =3v; t amb =25 c; unless otherwise speci?ed. symbol parameter min. typ. max. unit serial programming clock; clk t r , t f input rise and fall times - 10 40 ns t cy clock period 100 -- ns enable programming; e t start delay to rising clock edge 40 -- ns t end delay from last falling clock edge - 20 -- ns t w minimum inactive pulse width 4000 -- ns t su; e enable set-up time to next clock edge 20 -- ns register serial input data; data t su;dat input data to clock set-up time 20 -- ns t hd;dat input data to clock hold time 20 -- ns fig.3 serial bus timing diagram. handbook, full pagewidth mgg524 t su;dat t hd;dat t cy t f t r t end t su;e msb lsb address t start t w clk data e
1997 sep 03 11 philips semiconductors product speci?cation low-power dual frequency synthesizer for radio communications UMA1015AM typical performance characteristics handbook, full pagewidth 5.5 12 2 2.5 3.5 4 3 5 4.5 4 6 8 10 mgk784 v dd (v) i dd (ma) (3) (2) (1) fig.4 typical i dd as a function of v dd with both synthesizers on and voltage doubler disabled. (1) t amb = +90 c. (2) t amb = +25 c. (3) t amb = - 35 c. fig.5 typical charge pump current as a function of cpa voltage with t amb =25 c. handbook, full pagewidth 2.0 1.2 1.6 0 0.4 0.8 - 1.2 - 0.8 - 0.4 - 2.0 - 1.6 0 5 246 13 mgk783 v cpa (v) i cpa (ma) (2) (1) (2) (1) r set =15k w ; cra = 1. (1) v cc = 2.7 v. (2) v cc = 6.0 v.
1997 sep 03 12 philips semiconductors product speci?cation low-power dual frequency synthesizer for radio communications UMA1015AM fig.6 typical charge pump 3-state current as a function of cpa voltage. v cc =v dd =6v; r set =15k w ; cra = 1. (1) t amb = +25 c. (2) t amb = - 35 c. (3) t amb = +90 c. handbook, full pagewidth 4 2 0 - 4 - 2 0 5 246 13 mgk782 v cpa (v) i cpa (na) (2) (1) (3) fig.7 typical crystal input sensitivity as a function of input frequency with t amb =25 c. handbook, full pagewidth v xtalin (dbm) 10 0 - 30 - 50 05 35 30 25 20 - 20 - 40 - 10 15 10 mgk779 (1) (2) guaranteed area + 7 - 7 f xtalin (mhz) f xtalin externally terminated by 50 w load; ac-coupled. (1) v dd = 5.5 v. (2) v dd = 2.7 v.
1997 sep 03 13 philips semiconductors product speci?cation low-power dual frequency synthesizer for radio communications UMA1015AM fig.8 typical crystal input sensitivity as a function of input frequency with v dd = 5.5 v. handbook, full pagewidth 10 0 - 30 - 40 05 35 30 25 20 - 20 - 10 15 10 mgk780 (1) (2) f xtalin (mhz) v xtalin (dbm) guaranteed area + 7 - 7 (3) f xtalin externally terminated by 50 w load; ac-coupled. (1) t amb = - 35 c. (2) t amb = +25 c. (3) t amb = +90 c. fig.9 typical rf input sensitivity as a function of input frequency with t amb =25 c. handbook, full pagewidth 10 - 30 0 600 800 0 - 10 - 20 900 700 mgk781 100 200 300 400 500 1000 1100 1200 (1) (2) f rf (mhz) v rf (dbm) + 1 - 13 guaranteed area + 5 - 3.5 rf input externally terminated by 50 w load; ac-coupled. (1) v dd = 5.5 v. (2) v dd = 2.7 v.
1997 sep 03 14 philips semiconductors product speci?cation low-power dual frequency synthesizer for radio communications UMA1015AM fig.10 typical rf input sensitivity as a function of input frequency with v dd = 5.5 v. handbook, full pagewidth 10 - 30 0 600 800 0 - 10 - 20 900 700 mgk778 100 200 300 400 500 1000 1100 1200 f rf (mhz) v rf (dbm) (1) + 1 - 13 (2) (3) guaranteed area + 5 - 3.5 rf input externally terminated by 50 w load; ac-coupled. (1) t amb = - 35 c. (2) t amb = +25 c. (3) t amb = +90 c. fig.11 typical charge pump supply voltage as a function of v dd voltage with voltage doubler enabled. handbook, full pagewidth 5.5 6 4 2.5 3 5 5.5 5 4.5 v cc (v) v dd (v) 4.5 3.5 4 mgk777 (1) (2) (3) (1) t amb = - 35 c. (2) t amb = +25 c. (3) t amb = +90 c.
1997 sep 03 15 philips semiconductors product speci?cation low-power dual frequency synthesizer for radio communications UMA1015AM fig.12 typical rf input admittance (ic powered on). handbook, full pagewidth mgk785 0.2 0.5 1 2 5 0.2 0.5 1 2 5 10 10 0 0.2 0.5 1 2 5 10 + j - j (1) (2) (3) (1) real part: 500 w ; imaginary part: 1.4 pf; at 1.2 ghz. (2) real part: 800 w ; imaginary part: 1.1 pf; at 1.0 ghz. (3) real part: 830 w ; imaginary part: 0.9 pf; at 800 mhz. fig.13 typical crystal input admittance (ic powered on). handbook, full pagewidth mgk786 0.2 0.5 1 2 5 0.2 0.5 1 2 5 10 10 0 0.2 0.5 1 2 5 10 + j - j (1) (2) (1) real part: 7.8 k w ; imaginary part: 0.9 pf; at 3 mhz. (2) real part: 9.8 k w ; imaginary part: 1.0 pf; at 35 mhz.
1997 sep 03 16 philips semiconductors product speci?cation low-power dual frequency synthesizer for radio communications UMA1015AM application information fig.14 typical application block diagram. handbook, full pagewidth mgg533 main divider a main divider b reference divider phase comparator a phase comparator b tcxo voltage controlled oscillator splitter low-pass filter UMA1015AM transmit pll voltage controlled oscillator splitter low-pass filter receive pll power amplifier 1st if and remainder of receiver chain duplex filter 959 mhz 914 mhz low noise amplifier to demodulation modulated audio 1st mixer 856 mhz
1997 sep 03 17 philips semiconductors product speci?cation low-power dual frequency synthesizer for radio communications UMA1015AM fig.15 typical ct1 application. e width mgg534 3.9 k w 1 k w 1 k w 1 k w 10 k w 56 k w 15 w 18 w 18 w 18 w 56 w 18 w 18 w 18 w 56 w 1 nf 1 nf 1 nf 1 nf 1 nf 1 nf 100 nf 15 k w 120 w 39 k w 56 k w 27 k w 27 k w 39 k w 27 k w 27 k w 10 k w 18 w 33 w 18 w 100 nf 100 nf 3.3 nf 56 nf 1 nf 100 nf 1 nf 100 nf 15 w 100 nf 3.3 nf 56 nf 1 nf 100 nf p1 p2 cpa v dd1 hpd rfa dgnd f xtalin p3 f xtalo i set p0/ool v cc cpb rfb v dd2 agnd e data clk 1 2 3 4 5 6 7 8 9 10 11 12 20 19 18 17 16 15 14 13 UMA1015AM vcotx control vtcxo f osc gnd v ctr to power amplifier positive supply audio modulation positive supply 3-line bus positive supply vcorx control rf output to 1st mixer 856 mhz 959 mhz led positive supply positive supply rf output transmit frequency = 959 mhz. receive frequency = 914 mhz. 1st if = 58.1125 mhz. 2nd if = 455 mhz. vco sensitivity = 2 mhz/v. channel spacing = 12.5 khz. charge pump gain (cpa = cpb) = 1 ma/cycle.
1997 sep 03 18 philips semiconductors product speci?cation low-power dual frequency synthesizer for radio communications UMA1015AM package outline unit a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.15 0 1.4 1.2 0.32 0.20 0.20 0.13 6.6 6.4 4.5 4.3 0.65 1.0 0.2 6.6 6.2 0.65 0.45 0.48 0.18 10 0 o o 0.13 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.20 mm maximum per side are not included. 0.75 0.45 sot266-1 90-04-05 95-02-25 w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a x (a ) 3 a y 0.25 110 20 11 pin 1 index 0 2.5 5 mm scale ssop20: plastic shrink small outline package; 20 leads; body width 4.4 mm sot266-1 a max. 1.5
1997 sep 03 19 philips semiconductors product speci?cation low-power dual frequency synthesizer for radio communications UMA1015AM soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all ssop packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. wave soldering wave soldering is not recommended for ssop packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. even with these conditions, only consider wave soldering ssop packages that have a body width of 4.4 mm, that is ssop16 (sot369-1) or ssop20 (sot266-1) . during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1997 sep 03 20 philips semiconductors product speci?cation low-power dual frequency synthesizer for radio communications UMA1015AM definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
1997 sep 03 21 philips semiconductors product speci?cation low-power dual frequency synthesizer for radio communications UMA1015AM notes
1997 sep 03 22 philips semiconductors product speci?cation low-power dual frequency synthesizer for radio communications UMA1015AM notes
1997 sep 03 23 philips semiconductors product speci?cation low-power dual frequency synthesizer for radio communications UMA1015AM notes
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1997 sca55 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220, 5th floor, suite 51, 04552-903 s?o paulo, s?o paulo - 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